How To Eliminate And Reduce Failures in Surface Mount Technology

The manufacturing process, handling, and printed circuit assembly (PCA) testing can subject the package to a lot of mechanical stress that can cause failure. As grid array packages become larger, it becomes increasingly difficult to set safety levels for these steps.
For many years, packages have been characterized using a monotonic bending point test method, which is described in IPC/JEDEC-9702 Monotonic Flexural Characterization of Horizontal Interconnects on a Board. This test method describes the fracture strength of horizontal interconnects on a printed circuit board under bending loads. However, this test method does not determine the maximum allowable tension.
One of the challenges of the manufacturing process and assembly process, especially for lead-free PCAs, is that the stress on the solder joint cannot be measured directly. The most widely used metric to describe the risk of an interconnect component is the tension on the printed circuit board adjacent to the component, which is described in IPC/JEDEC-9704 Strain Testing Guide for Printed Wiring Boards.
Several years ago, Intel recognized this problem and began to develop a different test strategy to reproduce the worst-case bending conditions that occur in the field. Other companies such as Hewlett-Packard also realized the benefits of other test methods and began to consider similar ideas as Intel. The method has gained interest as more chip manufacturers and customers realize the value of determining the strain limit to minimize mechanically induced failures during manufacturing, handling and testing.
As the use of lead-free devices has expanded, user interest has also increased; many users face quality issues.
As interest has increased, IPC has felt the need to help other companies develop test methods that can ensure that BGAs are not damaged during manufacturing and testing. This work has been completed by the IPC 6-10d SMT Attachment Reliability Test Methods Working Group and the JEDEC JC-14.1 Packaged Device Reliability Test Methods Subcommittee.
The test method specifies eight contact points arranged in a circular array. The PCA with a BGA mounted in the center of the printed circuit board is mounted with the component facing down on the support pins and the load applied to the back of the BGA. The strain gages are placed adjacent to the component according to the recommended gage layout of IPC/JEDEC-9704.
The PCA is bent to the relevant tension levels and the extent of damage caused by flexing to these tension levels is determined by failure analysis. The tension level at which no damage occurs is determined by an iterative approach and is the tension limit.